1. Field
The present innovations relate to relate to provision, control and/or other aspects of clock signal operation(s).
2. Description of Related Information
Numerous computer and chip applications entail provision of a secondary clock signal that is synchronized to a reference clock. Many systems and techniques associated with Delay-Locked Loop (“DLL”) circuits, for example, include clock generators used to synchronize the output clocks with the input reference clock(s) for high-speed applications, such as with synchronous SRAM and DRAM. In general, high-speed digital systems often utilize clock generators with improved tuning or other features to improve performance.
As set forth below, one or more exemplary aspects of the present inventions may overcome such shortcomings and/or otherwise impart innovative aspects by, for example, providing circuitry with improved ability to maintain a locked state of a clock signal despite jitter or noise.
Additionally, with regard to additional aspects of the inventions herein, particularly with regard to higher speed operation, such aspects provide further innovation over existing circuitry/schemes of adaptive digital phase detector (DPD) that use a narrow lock-detect window to compare the rising-edges of the full-rate input reference clock (XCK) to these of the full-rate delay line feedback clock (FCK) before the DLL reaches its phase-locked state. Here, an advantage of comparing full-rate clocks before the DLL is locked is that the DLL lock-in time is minimized in that the rising edges of the full-rate clocks have the most edge transitions compared to these of the divided-down lower-rate clocks. Here, after the DLL reaches its phased-locked state, the lock-detect window of the adaptive DPD is automatically widened to avoid the unwanted out of phase lock condition caused by the random noise effects.
However, in certain situations, widening the lock-detect window may cause timing margin issues for high-speed full-rate clock operations. Therefore, previous innovations provided after the DLL reaches its phase-locked state is to divide down both the reference clock (XCK/N) and the feedback clock (FCK/N) to get more timing margin for widening the lock-detect window of the adaptive DPD. When the clock speed increases further, however, even usage of a narrow lock-detect wind before the DLL reaches its phase-locked state presents a timing margin challenge.
As set forth below, one or more exemplary aspects of the present inventions may overcome such shortcomings and/or otherwise impart innovative aspects by, for example, providing circuitry with improved ability to achieve lock and/or maintain a locked state of a clock signal despite jitter or noise.